| abstract |
Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding. |