http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8673707-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_67ccc4eed0e5d3851a872c33e9fe2178 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6055f9271d609df9fc38b16614400e9c http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c1e3d8364bf64e4ac6e1a9cd5df2bd54 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-51 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-338 |
| filingDate | 2011-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b51e32116264e1b77ac7fa05673220c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_962c6dce267c5100135c286836210697 |
| publicationDate | 2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8673707-B2 |
| titleOfInvention | Method for forming metal gate |
| abstract | A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9590073-B2 |
| priorityDate | 2010-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 45.