| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_77327ecac15edb7b22ece7b4ae0d2314
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_eb6396d0ddd446e269382b79de263011 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1089
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76867
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28556
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-45523 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate |
2011-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0e6b4bd7d4faea452989d3d03ecc5733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_05b6d2552c59999271f4c03f70cb10f9 |
| publicationDate |
2014-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8658533-B2 |
| titleOfInvention |
Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration |
| abstract |
An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013260553-A1 |
| priorityDate |
2011-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |