| abstract |
This description relates to an integrated circuit device including a semiconductor substrate, an under-bump-metallurgy (UBM) layer overlying the semiconductor substrate and a copper-containing pillar on the UBM layer. The copper-containing pillar includes a top surface, an upper sidewall surface adjacent to the top surface, and a lower sidewall surface adjacent to the UBM layer. The integrated circuit device further includes a barrier layer on the upper sidewall surface of the copper-containing pillar, wherein the barrier layer exposes the lower sidewall surface. The copper-containing pillar has a first height and the upper sidewall surface has a second height. The second height is greater than about 30 percent of the first height. |