| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ce34699ed60e7d0bbb223a12305e182b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6175bdc2d4b6333790b50c03c5541c2f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01046
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-04941
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00013
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01077
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01327 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3212 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44 |
| filingDate |
2010-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65a0a6141fd3ec0fc5d52d5a9f7c9386
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f05c59ee5e57eee3210c20bd23aae5b8 |
| publicationDate |
2013-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8617986-B2 |
| titleOfInvention |
Integrated circuits and methods for forming the integrated circuits |
| abstract |
A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9704888-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9530801-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10748968-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11251229-B2 |
| priorityDate |
2009-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |