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filingDate 2012-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2013-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2013-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8592916-B2
titleOfInvention Selectively raised source/drain transistor
abstract A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.
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