http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8513079-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c1e3d8364bf64e4ac6e1a9cd5df2bd54 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f823f036721e39c61ff0ced537273b8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_63c5c26e45c2b72e83bc817d1f371ad2 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2008-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af0229caa472b1cafba517079ee69be6 |
| publicationDate | 2013-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8513079-B2 |
| titleOfInvention | TFT SAS memory cell structures |
| abstract | A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N + polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N + polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P − polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P − polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P + polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally. |
| priorityDate | 2008-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 39.