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filingDate 2012-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_96a33f32f96cca48100d69220af506ea
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publicationDate 2013-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8445374-B2
titleOfInvention Soft error rate mitigation by interconnect structure
abstract A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
priorityDate 2007-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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