| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4b5f572b619f288fd9614079e64f20a8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1b3da50dee509962fb2332067d701beb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_201c3ac5b6e3d8120ef8337b3307f9e1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a5b18a44fdb82645bee1a16d127d9b79
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_005675464356b9717e3bceb9aae5d26c |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0466
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17728 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2011-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6aa03ae3d5b82a616031d6a45755ae4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a07fbbabd7f0d8bea29296f665f69391
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_baf8ed7d97f6bb4f658c9b8022c647ac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3d12c332ffcd4a1590415ed405494963
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5768ae74f3492f435af5d5447312802e |
| publicationDate |
2013-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8437187-B2 |
| titleOfInvention |
Semiconductor integrated circuit including memory cells having non-volatile memories and switching elements |
| abstract |
In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10388374-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9659646-B1 |
| priorityDate |
2011-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |