| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a930e85c11163036c83b14746a8deb7a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_48c62cb40536c196f2f1808cfe6d2ede
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f6b98febff278cbdab9bd6e710410d1d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ddad49c7e15b780da1abe3211e336712
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7b58e6f4ec607e83017d6fcd0e8bbe73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_50ceffc1bdf017d6ee0ed46300bbb2b4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fded53bccd7b0dbb758db50d6c8ae319 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-75 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2012-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eda416f40def03b3e6f4995f619cd236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8985a634db6c119395c69097aa13ed2c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b88a53025a3f431fb792aac4d575da48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_64ea91f5b4ad71f7f7aa043f021f0210
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee219e48e328ff7cb593ac40979ce79e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_903d46d3447b748959319db2052bd0d4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_15f27a1a17233285efadcf57b2104a47 |
| publicationDate |
2013-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8435864-B2 |
| titleOfInvention |
Process for single and multiple level metal-insulator-metal integration with a single mask |
| abstract |
A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask. |
| priorityDate |
2005-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |