http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8384187-B2

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filingDate 2010-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2013-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9e6a554ade568308307ca4db99ef50be
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publicationDate 2013-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8384187-B2
titleOfInvention Semiconductor device with shallow trench isolation
abstract To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
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priorityDate 2009-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 43.