http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8383469-B2

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00
filingDate 2011-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2013-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c0b964d067df815ca43ba51150a45501
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publicationDate 2013-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8383469-B2
titleOfInvention Producing transistor including reduced channel length
abstract A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. The first electrically conductive material layer has a thickness. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer. The second electrically conductive material layer, the first conductive material layer, and at least a portion of the substrate are conformally coated with an electrically insulating material layer having a thickness such that the thickness of the first conductive material layer is greater than the thickness of the electrically insulating material layer.
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Total number of triples: 43.