| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3eb56b9d0facf1fc36197d710ea90cba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_54e1eeb1034b8b105e131f0f69653242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f5741d97a927b09e0dabf6893f22058f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2567f407604e5aabd0e6d2fee7b5f01a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2011-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1157458e414dfb7640a5e79d3ef05818
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e05ff357c68bc6a118feb7dfeb6148c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30f4a0f5803466cbbd7885ab17031179
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bff0bae9f62fc73378f96f342017d31 |
| publicationDate |
2013-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8372706-B2 |
| titleOfInvention |
Semiconductor device fabrication method including hard mask and sacrificial spacer elements |
| abstract |
Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9548314-B1 |
| priorityDate |
2008-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |