http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8349734-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5b162a39be831be7e973803be6875c45 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40 |
| filingDate | 2010-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c61ae2d8f6c0855b3e63136ff688412 |
| publicationDate | 2013-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8349734-B2 |
| titleOfInvention | Integrated circuits having backside test structures and methods for the fabrication thereof |
| abstract | Embodiments of a method for fabricating an integrated circuit having a backside test structure are provided. In one embodiment, the method includes the steps of providing a semiconductor substrate, forming at least one Through-Silicon-Via (TSV) through the semiconductor substrate, forming a backside probe pad over the backside of the semiconductor substrate and electrically coupled to the at least one TSV, and forming a frontside bondpad over the frontside of the semiconductor substrate. The frontside bondpad is electrically coupled to the backside probe pad by the at least one TSV. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9443764-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9035369-B2 |
| priorityDate | 2010-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.