| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1e6a79ef138157683f2f00621b70a121
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6dc200d9cf25874ae3a9cd9904af13bf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a6e86a60a5f2284cef7a9c0d72d62f0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_86b9b4b07abce82e26232915122236af
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fe31a8cc7f049d3c3de7181b951e6a4e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-72 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0064
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0011 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-00 |
| filingDate |
2010-09-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2012-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1114eda5d3ba0a27b17cbc6c227905b4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2eb8757e17559427bbbd94c662be64b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_019b14a6e2e765fc2a39a2d5c2cdadec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_403a694ac627d02517c0a46571c569d3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70f64fd7092c3cd250dbfd7830139ba8 |
| publicationDate |
2012-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8320158-B2 |
| titleOfInvention |
Nonvolatile semiconductor memory device |
| abstract |
Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9779808-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9472282-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9530494-B2 |
| priorityDate |
2009-11-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |