http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8304782-B2

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filingDate 2012-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2012-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e6e055786cbf04a21ac7054576dcce87
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publicationDate 2012-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8304782-B2
titleOfInvention Array substrate
abstract An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017235200-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10840176-B2
priorityDate 2009-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 37.