| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_814a04c67ed8260fe369a3bce13db299
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e36d87bab8de5ca64e31db24c0b5a668
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a5c0a9cd2c22aa644908d93b1e348330
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6890cc834cf17bc5a39ed81d933357ec |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-307 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-02 |
| filingDate |
2010-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2012-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec3e2045cebda8188989359748849e0a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c362e8db88f2b025dccbe02cb20d629e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d49a16db5f7f9fd605430a8a3b36920d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f38044bfc66304325be8d5da905fcd3a |
| publicationDate |
2012-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8294472-B2 |
| titleOfInvention |
Reliability evaluation circuit and reliability evaluation system |
| abstract |
A reliability evaluation system comprises a reliability evaluation circuit and a reliability evaluation control circuit. The reliability evaluation circuit includes a stress device array and a stress voltage generating block configured to receive a control voltage, generate stress voltages generated by using two reference voltages, and apply the stress voltages to the unit devices in a stress mode via first I/O lines according to the control voltage. The stress device array includes the unit devices that are matrix-arrayed. Each of the unit devices has a first terminal connected to one of the first I/O lines and a second terminal connected to one of second I/O lines. The reliability evaluation control circuit is configured to generate the control voltage and the two reference voltages, and test reliability of the unit devices by using the first I/O lines and the second I/O lines. |
| priorityDate |
2009-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |