http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8242814-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1f0e34e46a28145785018887c61582d2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_35f1262fb3cece48903c8e01afe33636 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_763ab603a35636edd7c4ace140cea070 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00052 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-13 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-00006 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03B19-00 |
| filingDate | 2005-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2012-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_312e673db3d30437465e6fb688f170ab http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_915200dcb535bde1a70a542f964d78a5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_63d0e9a7db71a7e8ca1b800389d5c858 |
| publicationDate | 2012-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8242814-B2 |
| titleOfInvention | Clock generating circuit and clock generating method |
| abstract | A clock converting circuit ( 1 ) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit ( 2 ) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit ( 1 ) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit ( 1 ), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency. |
| priorityDate | 2004-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 63.