| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9d209a58c3f903510519ce5ef5b58f93
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1efe969dd2076734af3c6ea1191b5358
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0ac6461c5ee465de5977e21b98265642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ee41f730b05cecd1fecc14f2365bab90 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 |
| filingDate |
2008-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2012-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6efb777f7e6c6e7d4eaa9314c4918227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a08e5a7e9b86b47a0c2481c7559347f3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9f9c5afb0b46601d263f7f0e5a0f4c29
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_320e2c0c1f4080fd92295d9a821e300b |
| publicationDate |
2012-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8136017-B2 |
| titleOfInvention |
Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method |
| abstract |
Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10613931-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9646718-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012185753-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8935594-B2 |
| priorityDate |
2007-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |