| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-125
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28556 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2007-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2011-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2ea99a3a0f843bb9679ba9e058a113da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7889011662d7b4ce951f8e86a4939e3b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6068e1ce28e9d3f45cc809e9f7de97ec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_169b8d6980a6788ad51d3266b62da7b5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b261edbf4dd56426ba7da9cb0cdaf2a |
| publicationDate |
2011-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8039900-B2 |
| titleOfInvention |
Stacked semiconductor devices and methods of manufacturing the same |
| abstract |
The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug. |
| priorityDate |
2006-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |