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grantDate 2011-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d7118270e2a0807e411d494d3ac3e58b
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publicationDate 2011-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7982268-B2
titleOfInvention Dual-gate transistor and pixel structure using the same
abstract A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.
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Total number of triples: 36.