http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7977965-B1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0375
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-003
filingDate 2010-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2011-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_091c29f8da0d5866c0679bd07df90849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be82c2a64aaf5c7a6dbe37d2c8281a4a
publicationDate 2011-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7977965-B1
titleOfInvention Soft error detection for latches
abstract A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking. Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.
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priorityDate 2010-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578835

Total number of triples: 34.