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publicationNumber US-7958333-B2
titleOfInvention Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
abstract A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.
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