| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_70ca3ea7752cc2ae9b2687d93d702a99 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-3828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-5443 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06V10-955
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-57
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1737
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-575 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-499 |
| filingDate |
2006-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2010-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7de2ef0991a3fab5f29989f2fe73b31a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3b914260757d8f4761f0757fd3654a28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec70a6b0d523fd0bfa556111a7427c1c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0e9c552b8cbe0fd3d4d293f5c0bd806f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3d0f945688b93c342b2a760085d81df4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09c10b9dbe36b7ae865f6c9da2fc4be5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39b706e6a8ab4938c89e42d6aabd4c88 |
| publicationDate |
2010-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7853636-B2 |
| titleOfInvention |
Digital signal processing circuit having a pattern detector circuit for convergent rounding |
| abstract |
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9337841-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8543635-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011010410-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9183337-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9176928-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8479133-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8539011-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9081634-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8117247-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8010590-B1 |
| priorityDate |
2003-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |