http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7807529-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b809e16fc8e6cf409abc8b3376cda1d2 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2007-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aeecade52e38fdda12ec4ab899a68b0e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_28adf2b2533ec8c6c8eef53b84607166 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9022e2adffd11b29a3a9edf18fec030d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_720cd50a0e114b00cc73f61049980feb |
| publicationDate | 2010-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-7807529-B2 |
| titleOfInvention | Lithographically space-defined charge storage regions in non-volatile memory |
| abstract | Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11251189-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8513132-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11100988-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012270395-A1 |
| priorityDate | 2007-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.