| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2c78d80e9d323ad7c79518c80e0b8d16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1063 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-461
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763 |
| filingDate |
2008-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2010-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65d559ed2de875eba37ac5d405c8d458
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32d638b1d808b2d403cae82d5d53971d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4614641e581d076e5b6bc92a16ec9be2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3d5bcd32c1ace534d6e70835fe4aa06f |
| publicationDate |
2010-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7687381-B2 |
| titleOfInvention |
Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall |
| abstract |
Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8161637-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8853095-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9113562-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011016709-A1 |
| priorityDate |
2008-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |