http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7599218-B2

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filingDate 2007-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2009-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8124b6a51f1f1917fa1ac86b3e2b5bd
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publicationDate 2009-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7599218-B2
titleOfInvention Phase change memory comprising a low-voltage column decoder
abstract An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.
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priorityDate 2006-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 25.