http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7538577-B2

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17744
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-173
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00
filingDate 2005-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2009-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2ee41f23f3a658d3e4b4f9e8424ccb4
publicationDate 2009-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7538577-B2
titleOfInvention System and method for configuring a field programmable gate array
abstract A mechanism within an electronic system for adapting a field programmable gate array (FPGA) to a flash memory device that supports a synchronous serial peripheral interface (SPI) by coupling a small amount of MSI logic with the FPGA and the flash memory device, to configure the FPGA to a designed configuration state. The system comprises a first and additional FPGAs that support a serial configuration interface, SPI flash memory, and a parallel-load 8-bit shift register. SPI flash memory is initialized with a first configuration data pattern that is read from SPI flash memory and applied to the FPGAs during a first device configuration process resulting in the FPGAs each attaining a designed configuration state. The SPI flash memory is subsequently initialized with a second configuration data pattern by means of the first FPGA. Each FPGA attains another distinct designed configuration state by a second device configuration process.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111506529-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011153889-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8195857-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116414765-B
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Total number of triples: 30.