| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate |
2005-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_27ed07749846d1d883f4160609f290cd |
| publicationDate |
2009-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7495284-B2 |
| titleOfInvention |
Non-volatile memory devices with charge storage insulators and methods of fabricating such devices |
| abstract |
A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines. The conductive patterns penetrate the charge storage insulator and electrically connect with the active regions. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9245899-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8928092-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012168847-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8441063-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7691709-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8178916-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010237399-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008150046-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8779501-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9082653-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014015030-A1 |
| priorityDate |
2003-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |