| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_32cb5f206c2274eb01fd0449c54c3a70 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05571
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0557
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05001
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-131 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 |
| filingDate |
2006-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0a1a7cab8dd52f04f923256ee076a4cf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd417811d1c4af8a9aa5f4d206f668a3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2db1027a8a860e8f3239bd61db18dc8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa7052a22feb3b1bdbc07cc9ea770303 |
| publicationDate |
2009-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7476555-B2 |
| titleOfInvention |
Method of chip manufacturing |
| abstract |
A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; exposing a plurality of pads on the chips of the wafer; forming bumps on the pads of the chips of the wafer; performing tests from the bumps on the chips of the wafer. Alternatively, the present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; connecting a plurality of pads on the chips of the wafer to a plurality of corresponding pads on the substrate layer; planting bumps on the pads on the opposite side of the substrate layer; performing tests from the bumps on the substrate layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8653662-B2 |
| priorityDate |
2006-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |