http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7466998-B2

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filingDate 2004-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2008-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8203806ab9d9425fd481cdaee285af23
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publicationDate 2008-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7466998-B2
titleOfInvention Layout and architecture for reduced noise coupling between circuitry and on-chip antenna
abstract An integrated circuit layout and architecture for reduced noise coupling between circuitry and on-chip antenna for wireless communications includes a monolithic semiconducting substrate having a plurality of integrated devices including a transmitter and/or a receiver. At least one on-chip balanced antenna is formed in or on the substrate. A balanced antenna feed structure electrically connects the antenna to the transmitter or receiver. At least one integrated device is substantially symmetrically disposed on the substrate relative to the on-chip antenna(s). The device(s) selected for substantially symmetrically placement are preferably those which generate the largest noise coupling.
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Total number of triples: 28.