http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7428165-B2

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3427
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
filingDate 2006-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2008-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_656da08bdf2dfc75b76efc3f26ad9e8c
publicationDate 2008-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7428165-B2
titleOfInvention Self-boosting method with suppression of high lateral electric fields
abstract In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.
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