http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7317324-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1af8df51ce24ca931ae718fb747f6aa0 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31703 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3193 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3004 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317 |
| filingDate | 2004-11-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2008-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_552b1621ceffed693fbece3e15a3805c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f5225bdc2490f7990a0cd74bd30c1dde http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d29c7c15ba17ad2e5e9921a15e073ab0 |
| publicationDate | 2008-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-7317324-B2 |
| titleOfInvention | Semiconductor integrated circuit testing device and method |
| abstract | A plurality of resistors is connected to a plurality of output terminals of a semiconductor integrated circuit, respectively, and a predetermined voltage is applied to the plurality of resistors. Also, a predetermined operation pattern signal used to test functions of the semiconductor integrated circuit is input to a plurality of input terminals of the semiconductor integrated circuit. Thus, a total sum of amounts of currents caused to flow through the plurality of resistors, respectively, is measured. The total sum of amounts of currents thus measured is compared with a normal value of a total sum of amounts of currents which are measured in a non-defective sample which is used instead of the semiconductor integrated circuit and is verified in advance to normally operate. It is judged based on the comparison results whether or not the semiconductor integrated circuit is normal. As a result, whether or not the semiconductor integrated circuit is a non-defective or a defective can be simply judged without performing logic simulation and failure simulation. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9059190-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012170387-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8179154-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8709833-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010109674-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013161615-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I396855-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8520453-B2 |
| priorityDate | 2003-11-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.