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filingDate 2004-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2007-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2007-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7310754-B2
titleOfInvention Integrated test circuit, a test circuit, and a test method for performing transmission and reception processing to and from a first and a second macro block at a first frequency
abstract A macro block MB 2 including a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MB 1 at a clock frequency CF 1 . A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CF 2 that is lower than the frequency CF 1 , and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CF 3 that is lower than the frequency CF 1 . After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF 2 , it outputs the stored transmission data signal to the MB 2 at the frequency CF 1 . After the reception buffer RXB has stored the reception data signal from the MB 2 at the frequency CF 1 , it outputs the stored reception data signal to the terminal TPO at the frequency CF 3.
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