http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7268594-B1

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03B21-00
filingDate 2005-05-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2007-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9f8f264f44531ea5e5337ca94dd478e6
publicationDate 2007-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7268594-B1
titleOfInvention Direct digital synthesis with low jitter
abstract An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-staggered way. I Initially the frequency number N added into the accumulators is varied slightly for each accumulator by multiplying by a number, such as X/16 where X varies from 1 to 16 for each of 16 accumulator circuits. The accumulator circuits are further reconfigured so that the output of a register from a first accumulator provides feedback to the adder input in all of the accumulator circuits. The number of overflowing accumulator registers in a clock cycle will then indicate granularity spatially. To translate spatial granularity to time, a programmable delay circuit is connected to the output of each accumulator register.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10437946-B1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7952516-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022350600-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021145925-A1
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