http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7244652-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2004-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0825fbf1e24a5e4735ded8cd27f5a92c |
| publicationDate | 2007-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-7244652-B2 |
| titleOfInvention | Method of forming a split programming virtual ground SONOS memory |
| abstract | A method of forming an SPVG SONOS memory. First, a substrate having a well and a plurality of select gate structures is provided. Then, a plurality of sacrificial spacers are formed alongside each select gate structure, and an implantation process is performed to form a doped region in the well between any two adjacent select gate structures. Afterward, the sacrificial spacers are removed, and a composite dielectric layer is formed on the select gate structures and the substrate. Finally, a plurality of word lines are formed on the composite dielectric layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021391010-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11551738-B2 |
| priorityDate | 2004-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.