| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7f961fe8c8d1f1b4507f909c92cd9566 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2882
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11B20-1403 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31727
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-06 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R13-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C27-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11B20-14 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-06 |
| filingDate |
2003-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2007-01-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5fde8224a8ec447cec16dbac7f7c3043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3bbd3eedd0aa1f3c957e777dbc1872d7 |
| publicationDate |
2007-01-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7168020-B2 |
| titleOfInvention |
Circuit and method for testing embedded phase-locked loop circuit |
| abstract |
A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11609271-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022146576-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7676718-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9157957-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11070214-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007124634-A1 |
| priorityDate |
2002-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |