http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7157951-B1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_70ca3ea7752cc2ae9b2687d93d702a99
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-15013
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03H11-26
filingDate 2004-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2007-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98d9909946c44af3dc0edf536618dad8
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publicationDate 2007-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7157951-B1
titleOfInvention Digital clock manager capacitive trim unit
abstract A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009066382-A1
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