| abstract |
A CMOS integrated circuit ( 15 A-B-C) includes both relatively low-power ( 124, 126 ) and high-power ( 132, 134 ) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device ( 134 ) includes a heavily doped N-well drain region ( 70 ). A 20V, relatively high-power NMOS device ( 132 ) includes heavily doped P-type buried layers ( 76, 78 ) underneath the source ( 94 ) and drain regions ( 96 ) and spanning the gap between the P-well gate ( 90 F) and adjacent P-well isolation regions ( 46, 50 ). |