http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7099189-B1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fbb477cab6287ad715ceb612f63441ba
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1776
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0063
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00
filingDate 2004-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2006-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc1c5cb6a4a1dca59e20a0c9872cdb89
publicationDate 2006-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7099189-B1
titleOfInvention SRAM cell controlled by non-volatile memory cell
abstract First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.
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Total number of triples: 41.