http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7067414-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76825 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31633 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02211 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02167 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02323 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-469 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 |
| filingDate | 2000-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1c53fd1b96b9aa91f2371854dfe7903c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c73b3d9cffc54b9efda942ea9c283b9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52792ed49518ef57b15602c9e6255546 |
| publicationDate | 2006-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-7067414-B1 |
| titleOfInvention | Low k interlevel dielectric layer fabrication methods |
| abstract | A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure. After forming the dielectric layer, it is exposed to a plasma including oxygen at subatmospheric pressure effective to reduce the dielectric constant by at least 10% below what it was prior to the exposing. The exposing occurs without removing the substrate from the chamber between the depositing and the exposing, and pressure within the chamber is maintained at subatmospheric pressure between the depositing and the exposing. |
| priorityDate | 1999-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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