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filingDate 1998-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2006-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2006-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7043516-B1
titleOfInvention Reduction of add-pipe logic by operand offset shift
abstract The shifters ( 30, 32 ) that a floating-point processor ( 10 )'s addition pipeline ( 14 ) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction than for addition. As a result, the addition pipeline's rounding circuitry ( 160, 166 ) does not need to be capable of adding round bits in as many positions as it would without the shift difference, so it can be simpler and faster. Similarly, circuitry ( 164 a–g and 188 ) employed for normalization after addition and subtraction can be simpler because it does not have to implement as shift options.
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