http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7010475-B2

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b7317808024e524eea40a6c5a5ad6a22
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-33
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01B3-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50
filingDate 2003-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2006-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_794b6263261d22b175c8406af1474816
publicationDate 2006-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7010475-B2
titleOfInvention Derating factor determination for integrated circuit logic design tools
abstract An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.
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priorityDate 1999-05-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 41.