| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate |
2004-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2005-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d42b8f537ccd1d760b90e3cbc3c573fc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_764aebc5acad4c09f0a47128d2cb0d0b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ea123b81edf348abf284473ffce5e7e1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f9a427c6c94f0e4410e86aa7f4198049
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_212da6c57b97814b7e0edbdd0a0f34f6 |
| publicationDate |
2005-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6969660-B2 |
| titleOfInvention |
Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films |
| abstract |
The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7786524-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009294835-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7936005-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7518915-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9647060-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008073696-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017047397-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007171720-A1 |
| priorityDate |
2001-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |