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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-56
filingDate 2001-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2005-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d6fcb27bd82eff50249a3ade0cbffdf
publicationDate 2005-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6907385-B2
titleOfInvention Memory defect redress analysis treating method, and memory testing apparatus performing the method
abstract There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8977912-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008282107-A1
priorityDate 2000-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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