| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y30-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2001-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2005-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_59490c024c873facaaed33323ec9891b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5d95f137231163f3e6395c968e3368a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a18a98ce967dd5faabd640b60a7d183e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35059fee83e41777ea2d4100032d5aa1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_92d3e54b9bcae87bd892d8ce7365628b |
| publicationDate |
2005-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6902966-B2 |
| titleOfInvention |
Low-temperature post-dopant activation process |
| abstract |
A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate adjacent to the sidewalls spacers; laser thermal annealing to activate the source/drain regions; depositing a layer of nickel over the source/drain regions; and annealing to form a nickel silicide layer disposed on the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The annealing is at temperatures from about 350 to 500° C. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10361208-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7422968-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9735016-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010123448-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006024882-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7018888-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006024872-A1 |
| priorityDate |
2001-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |