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filingDate 2004-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2005-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e4707395b5cb9c1b3b00eb2c6320ca2
publicationDate 2005-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6879202-B2
titleOfInvention Multi-purpose digital frequency synthesizer circuit for a programmable logic device
abstract A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7551002-B1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007300112-A1
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