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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
filingDate 2001-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2004-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_083aefff0806fd387aa5837b95129926
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75880264aea710411984da064983b36a
publicationDate 2004-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6680254-B2
titleOfInvention Method of fabricating bit line and bit line contact plug of a memory cell
abstract A memory cell fabrication avoiding bit line encroaching. A first insulating layer and a first masking layer are formed on a semiconductor substrate with a diffused region. The first masking layer and the first insulating layer are defined to form a first trench above the diffusion region. A second masking layer is formed to fill the first trench, and a hole is formed by removing a portion of the second masking layer above the diffusion region. A bit line contact is formed by removing a portion of the first insulating layer beneath the hole to expose the diffusion region. A bit line contact plug is formed by filling the bit line contact with a first conductive layer. The residual second masking layer and the first masking layer are removed to form a second trench. A bit line is formed by filling the second trench with a second conductive layer.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016133511-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006194426-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011260225-A1
priorityDate 2001-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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