http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6633960-B1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5397fc5ff75ee49a454558b68b36baa
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0817
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08
filingDate 2000-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2003-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a247c6cde41adab10da7e509ac20af22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_602c2d54d671a258425ca564c276a668
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_220e6a4e73f8982ef6635776659b182b
publicationDate 2003-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6633960-B1
titleOfInvention Scalable directory based cache coherence protocol
abstract A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block. Eviction of a memory block copy held by an Owner processor in its cache requires a write of the memory block copy to its Home and update of the corresponding coherence directory. No reads of the Home processor directory or modification of other processor cache and main memory is required. The coherence controller in each processor is able to send and receive messages out of order to maintain the coherence of the shared data in cache and main memory. If an out of order message causes an incorrect next program state, the coherence controller is able to restore the prior correct saved program state and resume execution.</PTEXT>
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Total number of triples: 109.