http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6627973-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02271 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02129 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31625 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C16-40 |
| filingDate | 2002-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d012d68a4b6653bd17e8fa000751c0b4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97b22a44542905014bf649b2d9a83c11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4b8b4379e83d4881a6d4e19dde89570 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42e07c502b53a2d3068f52e4c3bc7bbd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_709fa93c23a12535325271e1a74a9bea |
| publicationDate | 2003-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-6627973-B1 |
| titleOfInvention | Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device |
| abstract | A method of eliminating voids in the interlayer dielectric material of 0.18-μm flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-μm flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-μm distance (gate-to-gate) as well as 0.38-μm distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD 0 layer of the 0.18-μm flash memory semiconductor device having a sound dopant concentration. |
| priorityDate | 2001-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.